1. Field of the Invention
The present invention relates to a signal processing circuit which is operable to determine timing for sampling an input signal.
2. Description of the Related Art
A phase adjustment circuit can be used to appropriately set timing for sampling a signal which cyclically changes. For example, the phase adjustment circuit determines a sampling phase for sampling and outputting, at predetermined periods of time, RGB digital signals, such as television broadcasting signals which are encoded according to the National Television Standards Committee (NTSC) system or the Phase Alternating Line (PAL) system.
FIG. 7 illustrates a sampling phase setting method according to a conventional phase adjustment circuit. An input signal SIG is a pulse signal that cyclically changes. A reference clock CLK is a pulse signal whose cyclic period is equal to a half of the cyclic period of the input signal SIG. The phase adjustment circuit performs sampling of the input signal SIG at a rise time (indicated by a white circle in the drawing).
In this case, the phase adjustment circuit adjusts a phase difference between the input signal SIG and the reference clock CLK so that the sampling timing accords with a maximum value and a minimum value of the input signal SIG in each cycle. Hence, as illustrated in FIG. 7, the phase adjustment circuit changes a phase θ of the reference clock CLK relative to the input signal SIG in increments of a predetermined amount (e.g., 20°), and obtains a phase θm where a difference between consecutive sampling values can be maximized. The phase adjustment circuit sets the obtained phase θm as a sampling phase difference between the input signal SIG and the reference clock CLK.
However, as illustrated in FIG. 8, the input signal SIG (i.e., a pulse signal) tends to overshoot or undershoot in the vicinity of rising or falling portions. In other words, the input signal SIG may include a noise component in a rising or falling portion. If the phase adjustment circuit obtains the phase θm (i.e., the sampling phase where the difference between consecutively obtained sampling values can be maximized) while changing the phase θ of the reference clock CLK relative to the input signal SIG, the sampling timing is adjusted to accord with the overshoot timing and the undershoot timing of the input signal SIG.
However, the overshoot timing is very close to the rising portion of the input signal SIG and the undershoot timing is very close to the falling portion of the input signal SIG. Therefore, if the phase difference between the input signal SIG and the reference clock CLK is slightly shifted, the sampling timing may match the rising portion and the falling portion of input signal SIG as illustrated in FIG. 9, and the sampling values may not accurately represent the amplitude of a pulse signal. For example, if the input signal SIG is a video signal, flicker effects of a regenerated video signal may occur if the sampling values fluctuate.